`include "include.v"

module seg7_basys_top (
  input wire        clk,
  input wire        rst_n,
  input wire        set,
  input wire  [1:0] anode_in,
  input wire  [3:0] seg_in,
  output wire [6:0] seg_out,
  output wire [3:0] anode_out,
  output wire       dp
);

wire clk_div;

reg [15:0] count;

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    count <= 1'b0;
  end else begin
    count <= count + 1'b1;
  end
end

assign clk_div = count[15];
	 
seg7_top i_seg7_top (
  .clk(clk_div),
  .rst_n(rst_n),
  .set(set),
  .seg_in(seg_in),
  .anode_in(anode_in),
  .anode_out(anode_out),
  .seg_out(seg_out),
  .dp(dp)
);

endmodule
